GBA Sound Hardware Overview

The elements of GBA sound

The GBA audio system has 6 channels. 4 of the channels provide synthensized audio (like square waves, and noise...); they are mostly for compatibility with GameBoy Color games. The other 2 channels are called "Direct Sound" channels, they accept raw data and convert it into speaker output. We will use the direct sound channels to output our final audio data.

Here is a list of the hardware registers used by the sound system:

4000060hSOUND1CNT_LChannel 1 (Square Wave 1) Sweep Register
4000062hSOUND1CNT_HChannel 1 (Square Wave 1) Duty/Length/Envelope
4000064hSOUND1CNT_XChannel 1 (Square Wave 1) Frequency/Control
4000068hSOUND2CNT_LChannel 2 (Square Wave 2) Duty/Length/Envelope
400006ChSOUND2CNT_HChannel 2 (Square Wave 2) Frequency/Control
4000070hSOUND3CNT_LChannel 3 (4-bit Wave Output) Stop/Wave RAM Select
4000072hSOUND3CNT_HChannel 3 (4-bit Wave Output) Length/Volume
4000074hSOUND3CNT_XChannel 3 (4-bit Wave Output) Frequency/Control
4000078hSOUND4CNT_LChannel 4 (Noise) Length/Envelope
400007ChSOUND4CNT_HChannel 4 (Noise) Frequency/Control
4000080hSOUNDCNT_LChannel Left/Right Volume/Enable
4000082hSOUNDCNT_HDirect Sound Control/Mixing
4000084hSOUNDCNT_XMaster Sound Enable
40000A0hFIFO_ADirect Sound A FIFO Access
40000A4hFIFO_BDirect Sound B FIFO Access

The last four registers are the ones we are interested in. Here is the format of SOUNDCNT_H

0-1Sound Channel 1-4 volume
2Direct Sound A Volume (0=50%, 1=100%)
3Direct Sound B Volume (0=50%, 1=100%)
4-7Not used.
8Direct Sound A - Enable Right Output
9Direct Sound A - Enable Left Output
10Direct Sound A - Timer Selection (0 = Timer0, 1 = Timer1)
11Direct Sound A - Reset FIFO (1 = reset FIFO status)
12Direct Sound B - Enable Right Output
13Direct Sound B - Enable Left Output
14Direct Sound B - Timer Selection (0 = Timer0, 1 = Timer1)
15Direct Sound B - Reset FIFO (1 = reset FIFO status)

Various bits... The first two bits control the volume of the old GBC channels; we're not interested in those. The next two bits control the volume of our direct sound channels. We want 100% volume, so we'll write "1,1" in those bits. We have 4 more bits to control each direct sound channel, the first two bits enable left/right speaker output (although the difference can only be heard with headphones since the GBA only has one built-in speaker). The third bit selects a hardware timer that will be used for the sampling rate. GBA has 4 hardware timers total, and the first two can be used for timing the sound. We will use timer 0 for our sampling-rate. The last bit is a reset flag; if you write '1' to it, then the FIFO will be cleared and reset. We will reset the FIFO at startup.

The next register (SOUNDCNT_X) is simple, it only has 1 bit that concerns us, the Master Enable bit.

0-3Sound Channel 1-4 Status
4-6Not used
7Master Sound Enable
8-15Not used

We have to set '1' in that bit before we will hear any sound.

Next we have the FIFO access registers. Internally, each direct sound channel has a FIFO that is 8 words wide (32 bytes). Data written to FIFO_A/FIFO_B gets pushed into the buffer and remains until it is feed into the sound circuit.

Feeding the data manually with the CPU will generate some huge overhead, there's another hardware feature that can help us out here: Direct Memory Access(DMA). The GBA has 4 DMA channels (DMA0,DMA1,DMA2,DMA3), 2 of them (DMA1,DMA2) have a special function that can be used to feed audio data to the FIFOs.

What we will do is set the destination address of the DMA to the sound FIFO registers, and set the source to our mixing buffer. Here's the control register bits for DMA1 and DMA2.

0-4Not used
5-6Destination Address Control (0=Increment,1=Decrement,2=Fixed,3=Increment/Reload)
7-8Source Address Control (0=Increment,1=Decrement,2=Fixed,3=Prohibited)
9DMA Repeat (0=Single transfer,1=Repeat until stopped)
10DMA Transfer Type (0=16bit, 1=32bit)
11Not Used
12-13Start Timing (0=Immediately,1=VBlank,2=HBlank,3=Sound Request)
14Request interrupt after transfer
15DMA Enable

For transferring sound data, we must set the source/destination control to increment, the repeat flag to on, the transfer type to 32-bit, and the start timing to 3 (Sound Request). I'm not really sure why the destination address control is supposed to be increment, but all the documents say to do this (and it works fine). We must also set the source address of the DMA channel to our wave buffer, and the destination address to the FIFO register.

When DMA1/DMA2 Start Timing is set to 3, then a transfer of 4 words (16 bytes) will occur when the sound FIFO contains 4 or less words.

There's one thing that's scary here, the DMA has NO way of restarting automatically when it has finished passing through our ring-buffer. What we must do is count the number of samples transferred and restart the DMA manually before it starts feeding the sound random data! (very critical timing)

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